1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to resistors or other non-transistor elements in complex integrated circuits that comprise field effect transistors including metal gate electrode structures.
2. Description of the Related Art
In modern integrated circuits, a great number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, and non-transistor components, such as resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are continuously reduced with the introduction of new circuit generations, thereby providing currently available integrated circuits with a high performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors and resistors, are typically formed in integrated circuits as required by the basic circuit layout. Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be improved, but also their packing density is significantly increased, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SOC).
Although transistor elements are the dominant circuit elements in highly complex integrated circuits and substantially determine the overall performance of these devices, other components, such as capacitors and resistors, are required, wherein the size of these passive circuit elements may also have to be adjusted with respect to the scaling of the transistor elements in order to not unduly consume valuable chip area. Moreover, the passive circuit elements, such as the resistors, may have to be provided with a high degree of accuracy in order to meet tightly set margins according to the basic circuit design. For example, even in substantially digital circuit designs, corresponding resistance values of so-called precision resistors have to be provided within tightly set tolerance ranges so as to not unduly contribute to operational instabilities and/or enhanced signal propagation delay. For example, in sophisticated applications, precision resistors may frequently be provided in the form of integrated polysilicon resistors, which may be formed above isolation structures so as to obtain the desired resistance value within the predefined tolerances without significantly contributing to parasitic capacitance, as may be the case in buried resistive structures, which may be formed within the active semiconductor layer. A typical polysilicon resistor may thus require the deposition of the basic polysilicon material, which may frequently be combined with the deposition of a polysilicon gate electrode material for the transistor elements. During the patterning of the gate electrode structures, the resistors may also be formed, the size of which may significantly depend on the basic specific resistance value of the polysilicon material and the type of dopant material and concentration that may be incorporated into the resistors so as to adjust the resistance values.
The continuous drive to shrink the feature sizes of complex integrated circuits has resulted in a gate length of field effect transistors of approximately 50 nm and less. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, referred to as a channel region, that is disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon forming a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration of the drain and source regions, the mobility of the charge carriers and, for a given transistor width, on the distance between the source region and the drain region, which is also referred to as channel length.
Presently, most complex integrated circuits are based on silicon due to the substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and due to the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations. One reason for the important role of silicon for the fabrication of semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows a reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows high temperature processes to be performed, as are typically required for anneal processes in order to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface. Consequently, in field effect transistors, silicon dioxide has preferably been used as a gate insulation layer which separates the gate electrode, frequently comprised of polysilicon, from the silicon channel region. Upon further device scaling, however, the reduction of channel length may require a corresponding adaptation of the thickness of the silicon dioxide gate dielectric in order to substantially avoid a so-called short channel behavior, according to which variability in channel length may have a significant influence on the resulting threshold voltage of the transistor. Aggressively scaled transistor devices with a relatively low supply voltage, and thus a reduced threshold voltage, therefore, suffer from a significant increase of the leakage current caused by the reduced thickness of a silicon dioxide gate dielectric. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm in order to maintain the required capacitive coupling between the gate electrode and the channel region. Although high speed transistor elements having an extremely short channel may, in general, preferably be used in high speed signal paths, whereas transistors with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by the direct tunneling of charge carriers through the ultra-thin silicon dioxide gate dielectric of the high speed transistor elements may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with thermal design power requirements for any type of complex integrated circuit system.
For this reason, replacing silicon dioxide as the base material for gate insulation layers has been considered, particularly for highly sophisticated applications. Possible alternative materials include such materials that exhibit a significantly higher permittivity, so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide, strontium titanium oxide, hafnium oxide, hafnium silicon oxide, zirconium oxide and the like.
Additionally, transistor performance may further be increased by providing an appropriate conductive material for the gate electrode in order to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface positioned between the gate dielectric material and the polysilicon material, thereby reducing the effective capacitance between the channel region and the gate electrode during transistor operation. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance, while additionally maintaining any leakage currents at an acceptable level. Since the non-polysilicon material, such as titanium nitride and the like, may be formed such that it may be in direct contact with the gate dielectric material, the presence of a depletion zone may thus be avoided, while, at the same time, a moderately high conductivity may be achieved by also using a highly conductive metal, such as aluminum, as a further electrode material.
As is well known, the threshold voltage of the transistor may depend on the overall transistor configuration, on a complex lateral and vertical dopant profile of the drain and source regions, the corresponding configuration of the PN junctions and on the work function of the gate electrode material. Consequently, in addition to providing the desired dopant profiles, the work function of the metal-containing gate electrode material also has to be appropriately adjusted with respect to the conductivity type of the transistor under consideration. For this reason, typically, metal-containing electrode materials may be used for N-channel transistors and P-channel transistors, which may be provided according to well-established manufacturing strategies in a very advanced manufacturing stage. That is, in these approaches, a gate layer stack comprising a dielectric and a polysilicon material in combination with other materials, if required, is provided and then patterned in order to form a gate electrode structure. Concurrently, corresponding resistors and other non-transistor elements, such as electronic fuses, may be patterned. Thereafter, the basic transistor configuration may be completed by forming drain and source regions, performing anneal processes and finally embedding the transistors in a dielectric material.
Next a process sequence follows, in which the top surface of the polysilicon material is exposed, which is typically accomplished by a first substantially selective chemical mechanical polishing (CMP) process, in which the interlayer dielectric material is planarized and thus removed. To this end, well-established polishing recipes are applied for removing silicon dioxide material, wherein the silicon nitride material, which is typically used as an etch stop layer in the contact levels of semiconductor devices, may act as a control layer together with the silicon nitride cap materials provided on top of the polysilicon material. Thereafter, the polishing recipe is changed so as to provide a substantially non-selective removal behavior so that silicon nitride material and silicon dioxide material may be removed with substantially the same removal rate, thereby preserving a substantially planar surface topography, while at the same time increasingly removing the dielectric cap material so as to finally expose the top surface of the polysilicon materials. After the exposure of the polysilicon material, highly selective etch recipes are applied, for instance on the basis of well-established wet chemical chemistries, thereby removing the polysilicon material in the gate electrode structures and also in the non-transistor structures, such as resistive structures, electronic fuses and the like. By depositing the high-k dielectric material, any appropriate work function metals and a highly conductive electrode metal, the gate electrode structures may be completed and thus have a desired superior electronic performance, while, on the other hand, the non-transistor structures may exhibit a quite different behavior compared to well-established resistors and electronic fuses formed on the basis of polysilicon material. That is, due to the high conductivity, any resistive structures, such as resistors and electronic fuses, would not properly function unless significant redesigns, for instance in terms of increasing the length of these structures, are applied. Any such significant redesigns, however, would result in undue consumption of chip area. For these reasons, frequently, non-transistor structures, such as resistors and electronic fuses, may be formed in the metallization system of the semiconductor device, thereby, however, also requiring significant redesigns and additional research and development efforts, since metal-based resistors and fuses may have a quite different electronic behavior.
In other conventional strategies, the non-transistor structures are provided in the active semiconductor layer so as to avoid any influence of the replacement gate approach on the non-transistor components. The incorporation of resistors and electronic fuses into the active semiconductor material may, however, result in a significant increase of the parasitic capacitance, which, thus, may significantly restrict the application of this concept in view of high frequency devices. Moreover, by forming electronic fuses in the active semiconductor material of bulk devices, i.e., of semiconductor devices in which the active silicon layer is not isolated from the remaining substrate material by a buried insulating layer that typically exhibits a significantly lower thermal conductivity compared to the bulk semiconductor material, a reliable programming of these electronic fuses may require significantly higher programming currents due to superior thermal coupling of the electronic fuse to the substrate material.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.